1. Technical Field
The present invention relates to a layout method of a semiconductor device, and more particularly, to a layout method of junction diodes for preventing damage caused by plasma charge.
2. Description of the Related Art
Due to increasing demands for high integration, very small patterns, and high performance semiconductor devices, various plasma processes are typically required in fabricating the semiconductor devices. The various plasma processes can include a dry etching process, a thin film deposition process using a plasma-enhanced chemical vapor deposition (PE-CVD) process, an ashing process, and a blanket etchback process. The dry etching process is generally used in fabricating highly integrated semiconductor devices because the dry etching process has an advantage in that even very small patterns can be processed to have an anisotropic etch characteristic, in comparison with a conventional wet etching process.
However, when the plasma process is applied to fabricate a metal-oxide-semiconductor (MOS) transistor, unequal charge is accumulated in the dry etching process for forming a gate line and a wiring line, or in the ashing process for removing a photosensitive pattern. Accordingly, a gate insulating layer can be damaged (referred to as “plasma damage”) due to the plasma charge which migrates to both edge side walls and a surface of a conductive layer forming the gate line or the wiring line. A defect of the semiconductor device caused by the plasma damage is mainly found during use by a customer after sale, whereas other initial defects can be screened in advance of delivery to the customer.
To address the plasma damage problem, a method of disposing a junction diode on a gate pattern has been developed. In other words, by using an NP diode for an N-type metal-oxide-semiconductor (NMOS) transistor and a PN diode for a P-type metal-oxide-semiconductor (PMOS) transistor, the unequal charge caused by the plasma process flows toward a circuit board through the junction diode rather than accumulating in undesired locations.
FIG. 1 illustrates a conventional layout method of a junction diode 150 for minimizing plasma damage. Referring to FIG. 1, for example, the junction diode 150 for minimizing plasma damage is provided in addition to providing a P-type metal-oxide-semiconductor (PMOS) transistor 110 and an N-type metal-oxide-semiconductor (NMOS) transistor 130, thereby forming an inverter circuit. A P-active layer 114a and a gate poly layer 116a included in the PMOS transistor 110 are disposed in an N-well layer 112. Bit poly layers 122a surrounding a contact layer 120a are disposed on the P-active layer 114a included in the PMOS transistor 110. One bit poly layer 122a on the P-active layer 114a connects with a metal layer 126a through a via layer 124a. A power supply voltage (VINT) is applied to the metal layer 126a. Another bit poly layer 122a on the P-active layer 114a connects with one bit poly layer 122b which is connected with an N-active layer 118b through a contact layer 120b which are included in the NMOS transistor 130. The P-active layer 114a forms a P-type doped active region and the N-active layer 118b forms an N-type doped active region.
A metal layer 126c to which a well bias voltage (VINTW) is applied, connects with a bit poly layer 122d through a via layer 124c and the bit poly layer 122d connects with an N-active layer 118a through a contact layer 120d. Thus, the N-active layer 118a forms a well guard ring in the N-well layer 112.
The N-active layer 118b and a gate poly layer 116b are included in the NMOS transistor 130. The bit poly layers 122b surrounding the contact layer 120b are disposed on the N-active layer 118b. Another bit poly layer 122b on the N-active layer 118b connects with a metal layer 126b through a via layer 124b and then connects with a P-active layer 114b through a contact layer 120e. A ground voltage (VSS) is applied to the metal layer 126b. The P-active layer 114b, to which the VSS is applied, forms a P-substrate bias.
The gate poly layers 116a and 116b, respectively included in the PMOS transistor 110 and the NMOS transistor 130, connect with a bit poly layer 122c through a contact layer 120c. The bit poly layer 122c connects with an N-active layer 118c through a contact layer 120f. The N-active layer 118c forms the NP junction diode 150 for preventing damage caused by plasma charge.
FIG. 2 illustrates an example wherein a dummy gate poly layer 116c is disposed in a region close to the gate poly layer 116b when the layout shown in FIG. 1 is disposed uniformly on a substrate. The dummy gate poly layer 116c is used in order to reduce step coverage in a gate poly region when the layout is formed repeatedly. Referring to FIG. 2, the dummy gate poly layer 116c overlaps with the N-active layer 118c forming the junction diode 150 for preventing damage caused by plasma charge, and hereinafter, this overlapped region is defined as region “A”. Although region “A” is not a transistor according to design rules, the region “A” may be misrecognized as a transistor region.
Therefore, a layout method of the junction diode 150 for preventing damage caused by plasma charge is needed for the dummy gate poly layer 116c such that it does not overlap with the N-active layer 118c, even though a unit layout is disposed uniformly on a substrate.